High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and g<sub>m</sub>/I<sub>D</sub> Methodology-Reference-Cited by-同舟云学术

High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and g_m/I_D Methodology

Published:2022-11 Issue:11 Volume:41 Page:4808-4820
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Chen Chen¹^ORCID,Wang Hongyi¹^ORCID,Song Xinyue²^ORCID,Liang Feng¹^ORCID,Wu Kaikai¹,Tao Tao¹

Affiliation:

1. Key Laboratory of Micro-Nano Electronics and System Integration of Xi’an City, Xi’an Jiaotong University, Xi’an, China

2. School of Information and Communication Engineering, Xi’an Jiaotong University, Xi’an, China

Funder

Joint Foundation of Key Laboratory of Shanghai Jiao Tong University-Xidian University, Ministry of Education

Department of Science and Technology of Shaanxi Province

China Electronics Technology Group Corporation, 24th Research Institute

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference40 articles.

3. Mine: Mutual information neural estimation;belghazi;arXiv 1801 04062,2018

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献