Design framework for inverter cascode transimpedance amplifier using Gm/ID based PSO applying design equations
Author:
Funder
United Arab Emirates University
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference51 articles.
1. Jespers P. The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches. Springer Science & Business Media, 2009.
2. Design technique for regulated cascode transimpedance amplifier using Gm/ID methodology;Elbadry;Microelectron J,2020
3. Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction;Akbari;Analog Integr Circ Sig Process,2015
4. A gm/ID-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier;Ou;IEEE Trans Circuits Syst II,2014
5. Experimental demonstration of Gm/Id based noise analysis;Ou;Circuits Syst,2014
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2. Automatic Design of a Cascoded-Inverter-Based Charge-Sensitive Amplifier Using gm/ID Technique and Particle Swarm Optimization in 28 nm CMOS;2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2023-06-29
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4. A 2.71‐pA/√Hz ultra‐low noise, 70‐dB dynamic range CMOS transimpedance amplifier with incorporated microstrip line techniques over extended bandwidth;International Journal of Circuit Theory and Applications;2022-10-12
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