Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture

Abstract

This paper presents a reconfigurable architecture for Network-on-Chip (NoC) design based on configuration switches. Reconfiguration is achieved by varying connection pattern between routers, depending on the currently running application. Mapping and reconfiguration strategies have been developed for the proposed architecture. In the mapping phase, cores in the combined application set are mapped to individual routers, minimizing the overall communication cost. In the second phase, for each application, configuration information for the switches (between the routers) are generated to optimize the communication cost further to suit the corresponding application. Exact methods, based on Integer Linear Programming (ILP), have been proposed for both the phases. Since ILP takes a large amount of CPU time, Particle Swarm Optimization (PSO)-based approaches have also been developed. The architecture and mapping strategies have been evaluated against benchmarks, considering communication cost, throughput, latency and network energy before and after reconfiguration. Significant improvements could be achieved via reconfiguration. Compared to the approaches reported in the literature, communication cost, throughput, latency and energy consumption values improve by 23.4%, 4%, 3% and 7%, respectively. These improvements come at a nominal increase in area overhead of 0.07%.