Mapping application‐specific topology to mesh topology with reconfigurable switches
Author:
Affiliation:
1. Department of Computer EngineeringAnkara UniversityAnkaraTurkey
2. Department of Computer EngineeringHacettepe UniversityAnkaraTurkey
3. Department of Computer EngineeringGazi UniversityAnkaraTurkey
Funder
Türkiye Bilimsel ve Teknolojik Araştirma Kurumu
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5202
Reference32 articles.
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3. Pan S.J. Cheng K.T.: ‘A framework for system reliability analysis considering both system error tolerance and component test quality’.Proc. of the Conf. on Design Automation and Test in Europe. Nice France (EDA Consortium) 2007 pp.1581–1586
4. Constantinides K. Plaza S. Blome J. et al.: ‘Bulletproof: a defect‐tolerant CMP switch architecture’.The Twelfth Int. Symp. on High‐Performance Computer Architecture 2006 Austin TX USA 2006 pp.5–16
5. Hu J. Marculescu R.: ‘Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures’.2003 Design Automation and Test in Europe Conf. and Exhibition Munich Germany 2003 pp.688–693
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1. Discrete Firefly Algorithm for Optimizing Topology Generation and Core Mapping of Network-on-Chip;Intelligent Automation & Soft Computing;2022
2. Power efficient network selector placement in control plane of multiple networks-on-chip;The Journal of Supercomputing;2021-10-25
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