Affiliation:
1. Department of Computer Science and Engineering, Indian Institute of Technology Madras 600 036, India
Abstract
The task or precedence graph formalism is a practical tool to study algorithm parallelization. Redundancy in such task graphs gives rise to numerous avoidable inter-task dependencies which invariably complicates the process of parallelization. In this paper we present an O(1) time algorithm for the elimination of redundancy in such graphs on Processor Arrays with Reconfigurable Bus Systemusing O(n4) processors, The previous parallel algorithm available in the literature for redundancy elimination in task graphs takes O(n2) time using O(n) processors.
Publisher
World Scientific Pub Co Pte Lt
Subject
Hardware and Architecture,Theoretical Computer Science,Software
Cited by
2 articles.
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