Affiliation:
1. Center for Integrated Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore S639798, Singapore
Abstract
In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic.
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture
Cited by
2 articles.
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