Novel Architecture for Low-Power CNTFET-Based Compressors

Abstract

Carbon nanotube field-effect transistors (CNTFETs) are excellent candidates for the replacement of traditional CMOS circuits. One of the most important modules in many arithmetic circuits is multiplier. Sometimes multipliers may occupy more area as well as consume high power which may cause speed reduction in the critical path. Compressors are important building blocks which are used in most multipliers. In this paper, a low-power architecture is proposed which can be used in compressor designs. The proposed architecture uses a low-power three-input XOR gate to reduce area, delay and power consumption. In order to evaluate the delay and power consumption of circuits, we have used four different types of compressors (3–2, 4–2, 5–2 and 7–2). These four designs were simulated using HSPICE simulation tool with 32-nm CMOS model based on 1-V and 1-GHz frequency operator. The results indicate that the proposed compressor architectures have less power–delay product (PDP) and power consumption in comparison with the existing proposed compressors.