High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads

Author:

Manikandan P.1,Bindu B.1ORCID

Affiliation:

1. School of Electronics Engineering, Vellore Institute of Technology, Vandalur-Kelambakkam Road, Chennai 600127, Tamil Nadu, India

Abstract

A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The proposed LDO does not require an external capacitor making it suitable for System-on-Chip (SoC) applications. The low-frequency PSR of the LDO varies with load current as the transconductance and output conductance of the power transistor depend on the load current. The proposed LDO is capable of maintaining a constant and high PSR for varying loads by using an adaptive network. The NMOS pass transistor in the adaptive network tracks the power-supply noise through the power transistor and bypasses this noise current through it to the ground. This helps to avoid the flow of this noise current through the load and thus the circuit can achieve high and constant PSR for varying loads. The LDO with adaptive network achieves very high power-supply rejections of [Formula: see text][Formula: see text]dB at low frequencies and [Formula: see text][Formula: see text]dB at 1[Formula: see text]MHz, for a load current of 4[Formula: see text]mA. This LDO is implemented in 0.18-[Formula: see text]m CMOS technology and consumes 1.35-mW quiescent power over the range of 1–10[Formula: see text]mA of the load current.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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1. Double-OTA External Capless Low-power LDO Regulator with Enhanced PSR and Transient Response;2023 5th Iranian International Conference on Microelectronics (IICM);2023-10-25

2. Design of High PSRR and Low Noise for LDO;2023 3rd International Conference on Intelligent Power and Systems (ICIPS);2023-10-20

3. A low power external capacitor‐less low drop‐out regulator with low over/undershoot voltage and high PSR;International Journal of Circuit Theory and Applications;2023-06-29

4. An Optimized Linear Regulator Circuit for Digital Chip;2023 8th International Conference on Intelligent Computing and Signal Processing (ICSP);2023-04-21

5. Design of LDO circuit based on curvature compensation reference closed-loop stability;AIP Advances;2023-01-01

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