An Optimized Linear Regulator Circuit for Digital Chip
Author:
Affiliation:
1. Dalian Neusoft University of Information,School of Intelligence and Electronic Engineering,Dalian,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10248366/10248210/10248753.pdf?arnumber=10248753
Reference8 articles.
1. Fast‐transient high‐performance 0.18 μm CMOS LDO for battery‐powered systems
2. An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique
3. High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads
4. A capacitorless low-dropout regulator with enhanced slew rate and 4.5- $$\upmu \hbox {A}$$ μ A quiescent current
5. Low power output-capacitorless class-AB CMOS LDO regulator
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