IMPROVED MODIFIED FAT-TREE TOPOLOGY NETWORK-ON-CHIP

Abstract

C-based cycle-accurate simulations are used to evaluate the performance of a Network-on-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformly-distributed destination addresses and non-uniformly-distributed destination addresses. A simple new traffic model has been developed for generating non-uniformly-distributed destination addresses. This model is general enough to be used in developing new NoC architectures and captures universally accepted place-and-route methodologies. Simulation results are used to illustrate how the hardware resources of a modified Fat Tree NoC can be minimized without affecting the network performance. The performance of a NoC with regular Mesh topology was also evaluated for comparison with the modified Fat Tree topology.