Influence of Cell Design and Gate-to-Source Voltage on Avalanche Robustness of SiC MOSFET Integrated JBS Diode

Abstract

In this work, 1200 V SiC JMOS devices with different Wsch (2 μm, 2.5 μm and 3 μm) are fabricated. The single unclamped inductive switching (UIS) tests under different Vgs_off (-5 V and 0 V) are carried out to investigate the avalanche capability. The avalanche robustness among various Wsch under same Vgs_off is also compared and analyzed by simulation. The different failure mechanisms between different Vgs_off are studied by failure analysis and simulation. The method of improving avalanche ruggedness of JMOS is proposed.