Demonstration of SiC Trench Gate MOSFETs with Narrow Cell Pitch Using Source Self-Aligned Process

Abstract

The SiC trench gate MOSFET with narrow cell pitch is demonstrated using a process in which the n+ source is self-aligned to the trench gate. A minimum cell pitch of 1.6 μm, which is difficult to achieve using the conventional device structure, is easily fabricated by applying a deep n+ source and a buried interlayer dielectric structure. The cell pitch reduction indicates a beneficial trend that contributes to a decrease in the specific on-resistance and an increase in the breakdown voltage. The process and structure are promising for further improving SiC power device characteristics.