Optimization of TaSi₂ Processing for 500 °C Durable SiC JFET-R Integrated Circuits

Abstract

Experiments are described towards optimizing tantalum silicide (TaSi2) interconnect metal film sputter-deposition and annealing in a manner compatible with the NASA Glenn two-layer interconnect silicon carbide (SiC) JFET-R IC process flow. Films deposited on 100 mm diameter wafers were investigated over a range of film thickness, sputter deposition, and post-deposition anneal conditions. An optimized process that achieved TaSi2 films free of cracking and morphological defects while nearly halving post-anneal stress was developed and will be used for completing the interconnect fabrication of prototype IC Gen. 12 SiC JFET-R ICs.