Interfacial Delamination Validation on Fan-Out Wafer-Level Package Using Finite Element Method

Abstract

Fan-out wafer-level package is a very promising packaging technology with good thermal and electrical performance. The fan-out wafer-level package exhibits beneficial features such as low profile, high I/O density, low cost, and efficient computing. The package experiences large temperature variations in the assembly phase which causes internal stresses. In particular, the mismatch between the coefficient of thermal expansion of the epoxy molding compound and the substrate due to the cool down phase of the cure process causes the internal stresses in the package. These internally induced stresses result to interfacial delamination. In this study, the interfacial delamination on a fan-out wafer-level package right after post mold cure of glass wafer was evaluated using the stress-based damage index through the finite element analysis in the ANSYS software package. The model was validated by comparing the simulation result of the glass wafer warpage to the existing experimental result from literature. From the warpage simulation of the glass wafer, the region on the package with high stress level was located and examined which may cause interfacial delamination. The maximum shear stress and principal stress at the epoxy molding compound and the Silicon chip interface was found to exceed the adhesion strength. This indicates that the interfacial delamination is inevitable. The information obtained from the stress analysis of molded wafer provides insight for the possible interfacial failure of fan-out wafer-level package in the individual package when subjected to thermomechanical loads.