Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging-Reference-Cited by-同舟云学术

Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging

Published:2018-01 Issue: Volume:80 Page:14-23
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Chiu Tz-Cheng^ORCID,Yeh En-Yu

Funder

Ministry of Science and Technology, R.O.C.

ASE Group

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference23 articles.

1. Wafer level packaging (WLP): fan-in, fan-out and three-dimensional integration;Xuejun,2010

2. Fan-out: Technologies & Market Trends 2016 Report;Azémar,2016

3. 24″×18″ fan-out panel level packing;Braun,2014

4. The novel liquid molding compound for fan-out wafer level package;Kan,2016

5. Study on process induced wafer level warpage of fan-out wafer level packaging;Che,2016

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