1. C. Richard, et. al.; Barrier and seed layer wet etching, Solid State Phenomena, Vol. 103~104 (2005), p.361~364.
2. G. Delgadino, A. Zhao, et. al.; Tungsten hard mask damascene integration scheme for 65nm, 206th Meeting of the Electrochemical Society/2004 Fall Meeting of the Electrochemical Society of Japan, 2004, p.922.
3. Cheng Ming Weng, Miao Chun Lin, Ren Huang, US patent pending.
4. J. Segura and C. Hawkins, CMOS Electronics, How It Works, How It fails, (Wiley Interscience, A John Wiley & Sons, INC., Publication). 2004. p.159~178. (a) (b) 200nm 200nm (c) 200nm.