Metal Hard Mask Employed Cu/Low k Film Post Ash and Wet Clean Process Optimization and Integration into 65nm Manufacturing Flow

Author:

Lin Miao Chun1,Wang Mei Qi1,Lai Joe1,Huang Ren1,Weng Cheng Ming1,Liao J.H.1,Tang Jian She2,Weng Ching Hwa2,Lu Wei2,Chen Han Wen2,Lee John T.C.2

Affiliation:

1. Tainan Science Park

2. Applied Materials

Abstract

As 65nm technology in mass production and 45nm technology under development, post etch ash and cleaning faces new challenges with far more stringent requirements on surface cleanliness and materials loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. We have optimized a post etch ash process and developed a novel aqueous solution (AQ) based single wafer cleaning process to address these new defect modes. Physical characterization results and process integration electrical data are presented in this paper.

Publisher

Trans Tech Publications, Ltd.

Subject

Condensed Matter Physics,General Materials Science,Atomic and Molecular Physics, and Optics

Reference4 articles.

1. C. Richard, et. al.; Barrier and seed layer wet etching, Solid State Phenomena, Vol. 103~104 (2005), p.361~364.

2. G. Delgadino, A. Zhao, et. al.; Tungsten hard mask damascene integration scheme for 65nm, 206th Meeting of the Electrochemical Society/2004 Fall Meeting of the Electrochemical Society of Japan, 2004, p.922.

3. Cheng Ming Weng, Miao Chun Lin, Ren Huang, US patent pending.

4. J. Segura and C. Hawkins, CMOS Electronics, How It Works, How It fails, (Wiley Interscience, A John Wiley & Sons, INC., Publication). 2004. p.159~178. (a) (b) 200nm 200nm (c) 200nm.

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