Current-Voltage Characteristics of Side-Gated Silicon Nanowire Transistor Fabricated by AFM Lithography

Abstract

Silicon nanowire transistor (SiNWT) was fabricated by using a silicon nanowire as a channel which directly connected to the source (S) and drain (D). In this work, a side gate (G) formation was used to develop a transistor structure. AFM lithography was performed to create the nanoscale oxide patterns via local anodic oxidation (LAO) mechanism. A conductive AFM tip was used to grow localized oxide layer on the surface of silicon on insulator (SOI) substrate by the application of voltage between tip and substrate. Other parameters that will influence the patterning process such as tip writing speed, relative air humidity, anodization time and substrate orientation were controlled. The patterned structure was etched with tetramethylammonium hydroxide (TMAH) and hydrogen fluoride (HF) acid to remove the uncovered silicon layer and silicon oxide mask patterns, respectively. The surface topography and dimension of the fabricated SiNWT was observed under AFM. Obtained results for the channel thickness, channel length and the distance between the channel and side gate are 32.92 nm, 7.63 µm and 108.07 nm, respectively. Meanwhile, the I-V characteristics of fabricated SiNWT measured at positive gate voltages are similar to p-type FET characteristics.