Analysis of 4H-SiC MOS Capacitors on Macro-Stepped Surfaces

Abstract

In this study, we compare the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (<1nm), surface with one with a roughness of ~40nm, characterized by big macrosteps and large terraces. We compared the two surfaces for different thermal oxide thicknesses, ranging from dOx = 3.6 nm to dOx = 32 nm. The extracted interface state traps (Dit) shows a small, but systematic, decrease of ~10-15 % for the samples with macrosteps.