Modeling and Analysis of Material Removal Characteristics in Silicon Wafer Double Side Polishing

Abstract

As advancing technologies increase the demand for yield and planarity in integrated circuits, wafers have become larger and their specifications more stringent. Flatness, thickness variation and nanotopography have emerged as important concerns in the wafering process. Double side polishing has been adopted as a solution to these problems. This paper focuses on the material removal characteristics and wafer profile variation during Si double side polishing. A polishing experiment to investigate Si removal characteristics according to process parameters was carried out in a single head rotary polisher equipped with a monitoring system for friction force. It was found that the material removal rate is related to friction energy rate, and the polishing state was transited and divided into three conditions according to pressure. On the basis of the experimental results, the wafer profile variation in double side polishing was modelled and simulated according to pressure. The friction energy was calculated to find the material removal amount across the wafer. With the conversion of calculated friction energy to the material removal amount, wafer profile variation was simulated. As a result, the wafer profile variation and its range were increased with a pressure increase, and originated from the position near the wafer edge.