Modeling of Threshold Voltage Hysteresis in SiC MOSFET Device

Abstract

In this paper, we report on the simulation results of instability threshold voltage of SiC MOSFET device. Hysteresis cycles of threshold voltage suggest that trapping and detrapping phenomena of electrons from the SiC layer into the oxide traps occur. Experiment suggests that positive threshold voltage shifts (ΔVth) caused by a positive stress voltage to the gate, are almost fully recovered by applying negative stress voltage. This work assumes uniform trap densities extending from SiC interface at a limited depth into oxide.