A Simulation Study on the Impact of InP Barrier on InGaAs/InP Hetero Junction Gate all around MOSFET

Abstract

In this work, we have analyzed the digital and analog performance for InGaAs/InP heterojunction Gate all around MOS structure. A detailed study on the impact of Barrier thickness on different analog and digital performance for an InGaAs/InP hetero structure GAA MOSFET is carried out by using TCAD device simulation. The electrical parameters such as surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried out and analyzed by varying the barrier thickness from 1 nm to 4 nm. Based on the simulation results it is investigated that the effect of the all electrical parameters in the nanoscale devices. It has been seen from the presented results that the influence of barrier thickness variation gives the notable improvement in drain current. The impact of InGaAs/InP hetero structure and barrier thickness variation claims GAA MOSFET as a promising candidate for VLSI applications. Keywords: Heterojunction, InGaAs/InP, TCAD, Analog parameters.