Recovery of Bipolar-Current Induced Degradations in High-Voltage Implanted-Gate Junction Field Effect Transistors

Abstract

Electron-hole recombination-induced stacking faults have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effects of bipolar injection induced stacking faults on the electrical characteristics of p+ ion-implanted high-voltage vertical-channel JFETs with 100-μm drift epilayers. The JFETs were stressed at a fixed gate-drain bipolar current density of 100 A/cm2 for five hours, which led to degradation of the forward gate-drain p-n junction and on-state conduction. The degradation was fully reversed by annealing at 350 °C for 96 hours. Forward and reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Non-degraded characteristics remain unaffected by annealing events. Consequently, should minority carrier injection occur in JFETs operating at elevated temperatures no stacking fault induced degradations are expected. This eliminates the need for specialty substrates with suppressed densities of basal plane dislocations in the fabrication of high-voltage SiC JFETs for high temperature applications.