Affiliation:
1. Mitsubishi Electric Corporation
Abstract
MOS interface traps are characterized by device simulation on the basis of temperature dependence of lateral MOS-TEG devices on the same Al-implanted p-type region as vertical device. The simulation shows fairly large Dit in SiO2/4H-SiC interface, corresponding to the suggested trap density inside the conduction band. Temperature dependence of on-resistance is explained by application of evaluated interface properties to calculation of current voltage properties of vertical DMOSFET.
Publisher
Trans Tech Publications, Ltd.
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science
Cited by
4 articles.
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