Impact of mutual inductance on timing in nano-scale SoC-Reference-Cited by-同舟云学术

Impact of mutual inductance on timing in nano-scale SoC

Published:2018 Issue:11 Volume:15 Page:20180376-20180376
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Sakata Kazuyuki¹²,Hasegawa Takashi³²,Ichikawa Kouji⁴²,Kanamoto Toshiki⁵²

Affiliation:

1. Renesas Electronics Corp.

2. JEITA Semiconductor & System Design Technical Committee

3. Sony LSI Design

4. DENSO CORPORATION

5. Hirosaki University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/15/11/15_15.20180376/_pdf

Reference17 articles.

1. [1] K. Banerjee and A. Mehrotra: “Analysis of on-chip inductance effects for distributed RLC interconnects,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21 (2002) 904 (DOI: 10.1109/TCAD.2002.800459).

2. [2] T. Sato, et al.: “Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF,” The ASP-DAC Asia and South Pacific Design Automation Conference (2003) 149 (DOI: 10.1109/ASPDAC.2003.1195008).

3. [3] A. Roy, et al.: “Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patterns,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18 (2010) 338 (DOI: 10.1109/TVLSI.2008.2011911).

4. [4] T. Murgan, et al.: “Timing and power consumption in high-speed very deep sub-micron on-chip interconnects,” J. Integr. Circuits Syst. 1 (2006) 25.

5. [5] M. S. Ullah and M. H. Chowdhury: “Analytical models of high-speed RLC interconnect delay for complex and real poles,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 1831 (DOI: 10.1109/TVLSI.2017.2654921).

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