A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis

Author:

Kanamoto Toshiki1,Kasai Koki1,Hatakeyama Kan1,Kurokawa Atsushi1,Nagase Tomoyuki1,Imai Masashi1

Affiliation:

1. Graduate School of Science and Technology, Hirosaki University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference35 articles.

1. [1] R.H. Dennard, et al.: “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits 9 (1974) 256 (DOI: 10.1109/JSSC.1974.1050511).

2. [2] Semiconductor Industry Association: International technology roadmap for semiconductors (2013) https://www.semiconductors.semiconductors-itrs/.

3. [3] K.T. Tang and E.G. Friedman: “Estimation of transient voltage fluctuations in the CMOS-based power distribution networks,” The 2001 IEEE International Symposium on Circuits and Systems 5 (2001) 463 (DOI: 10.1109/ISCAS.2001.922085).

4. [4] K.T. Tang and E.G. Friedman: “On-chip ΔI noise in the power distribution networks of high speed CMOS integrated circuits,” 13th Annual IEEE International ASIC/SOC Conference (2000) 53 (DOI: 10.1109/ASIC.2000.880675).

5. [5] A. Waizman, et al.: “CPU power delivery impedance profile resonances impact on core FMAX,” 2006 IEEE Electrical Performance of Electronic Packaging (2006) 119 (DOI: 10.1109/EPEP.2006.321206).

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