An efficient controlled LFSR hybrid BIST scheme

Author:

Liu Tieqiao1,Liu Peng2,Liu Yi1

Affiliation:

1. Hangzhou Dianzi University

2. Guangdong University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. [1] A. Jas, et al.: “Weighted pseudo-random hybrid BIST,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12 (2004) 1277 (DOI: 10.1109/TVLSI.2004.837985).

2. [2] S. Wang, et al.: “A low overhead high test compression technique using pattern clustering with N-detection test support,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18 (2010) 1672 (DOI: 10.1109/TVLSI.2009.2026420).

3. [3] E. Kalligeros, et al.: “Reseeding-based test set embedding with reduced test sequences,” Proc. of Int’l Symp. Quality Electronic Design (2005) 226 (DOI: 10.1109/ISQED.2005.105).

4. [4] C. Hu, et al.: “BIST structure and test pattern generation method based on controlled LFSR,” Journal of Circuits and Systems 3 (2002) 13 (DOI: 10.3969/j.issn.1007-0249.2002.03.003).

5. [5] Z. You, et al.: “A scan disabling-based BAST scheme for test cost reduction,” IEICE Electron. Express 8 (2011) 1367 (DOI: 10.1587/elex.8.1367).

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1. Hybrid non scan with built-in self-test for fault coverage improvement;5TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC, COMMUNICATION AND CONTROL ENGINEERING (ICEECC 2021);2023

2. A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications;2020 IEEE 29th Asian Test Symposium (ATS);2020-11-23

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