A scan disabling-based BAST scheme for test cost reduction
Author:
Affiliation:
1. College of Information Science & Engineering, Hunan University
2. China Academy of Machinery Science & Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://www.jstage.jst.go.jp/article/elex/8/16/8_16_1367/_pdf
Reference11 articles.
1. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes
2. [2] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel-Huffman test-data compression for IP cores with multiple scan chains,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 7, pp. 926-931, 2008.
3. [3] G. Dai, Z. You, J. Kuang, and J. Huang, “DCScan: A Power-Aware Scan Testing Architecture,” IEEE Proc. ATS, pp. 343-348, 2008.
4. [4] S. Donglikar, M. Banga, M. Chandrasekar, and M. S. Hsiao, “Fast Circuit Topology Based Method to Configure the Scan Chains in Illinois Scan Architecture,” IEEE Proc. ITC, Paper 18.3, 2009.
5. Embedded Deterministic Test
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4. A scan disabling-based BAST scheme for test cost and test power reduction;IEICE Electronics Express;2012
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