A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard
Author:
Affiliation:
1. School of Physical Science and Technology, University of Sichuan
2. Science and Technology on Analog Integrated Circuit Laboratory
3. School of Electrical and Electronic Engineering, Chongqing University of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/15/15/15_15.20180617/_pdf
Reference10 articles.
1. [1] M. Fujishima, et al.: “A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link,” IEICE Electron. Express 10 (2018) 0125 (DOI: 10.1587/elex.15.20170764).
2. [2] A. Aghighi, et al.: “A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors,” ICECS (2016) 217 (DOI: 10.1109/ICECS.2016.7841171).
3. [3] Y.-H. Kim, et al.: “An 11.5 Gb/s 1/4th baud-rate CTLE and two-tap DFE with boosted high frequency gain in 110-nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015) 588 (DOI: 10.1109/TVLSI.2014.2314147).
4. [4] S. Luetkemeier, et al.: “Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples,” IEICE Electron. Express 10 (2014) 484 (DOI: 10.1587/elex.11.20140274).
5. [5] W.-S. Kim and W.-Y. Choi: “A 10-Gb/s low-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram,” IEICE Electron. Express 10 (2013) 20130030 (DOI: 10.1587/elex.10.20130030).
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