A novel highly reliable and low-power radiation hardened SRAM bit-cell design-Reference-Cited by-同舟云学术

A novel highly reliable and low-power radiation hardened SRAM bit-cell design

Published:2018 Issue:3 Volume:15 Page:20171129-20171129
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Lin Dianpeng¹²,Xu Yiran¹²,Liu Xiaonian¹²,Zhu Wenyi¹²,Dai Lihua¹²,Zhang Mengying¹²,Li Xiaoyun¹²,Xie Xin¹²,Jiang Jianwei¹²,Zhu Huilong¹²,Zhang Zhengxuan¹,Zou Shichang¹

Affiliation:

1. Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences

2. University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/15/3/15_15.20171129/_pdf

Reference13 articles.

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2. [2] J. Guoet al.: “Soft error hardened memory design for nanoscale complementary metal oxide semiconductor technology,” IEEE Trans. Reliab. 64 (2015) 596 (DOI: 10.1109/TR.2015.2410275).

3. [3] R. Rajaeiet al.: “Design of robust SRAM cells against single-event multiple effects for nanometer technologies,” IEEE Trans. Device Mater. Rel. 15 (2015) 429 (DOI: 10.1109/TDMR.2015.2456832).

4. [4] T. Calinet al.: “Upset hardened memory design for submicron CMOS technology,” IEEE Trans. Nucl. Sci. 43 (1996) 2874 (DOI: 10.1109/23.556880).

5. [5] S. M. Jahinuzzamanet al.: “A soft error tolerant 10T SRAM bit-cell with differential read capability,” IEEE Trans. Nucl. Sci. 56 (2009) 3768 (DOI: 10.1109/TNS.2009.2032090).

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