A single ended 6T SRAM cell design for ultra-low-voltage applications-Reference-Cited by-同舟云学术

A single ended 6T SRAM cell design for ultra-low-voltage applications

Published:2008 Issue:18 Volume:5 Page:750-755
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Singh Jawar¹,Pradhan Dhiraj K.¹,Hollis Simon¹,Mohanty Saraju P.²

Affiliation:

1. Department of Computer Science, University of Bristol

2. Department of Computer Science, University of North Texas

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/5/18/5_18_750/_pdf

Reference9 articles.

1. [1] International Technology Road map for Semiconductors, Test and Test Equipments, 2006, [Online] http://public.itrs.net/

2. [2] N. S. Kim, K. Flautner, D. Blaauw, and T Mudge, “Circuit and microarchitectural techniques for reducing cache leakage power, ”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 3, pp. 167-184, 2004.

3. Single-ended SRAM with high test coverage and short test time

4. [4] A. Wang and Chandrakasan, “A 180mV FFT processor using sub-threshold circuit techniques, ” Proc. IEEE ISSCC Dig. Tech. Papers, pp. 229-293, 2004.

5. [5] R. E. Aly, M. I. Faisal, and M. A. Bayoumi, “Novel 7T sram cell for low power cache design, ”SOC Conference, 2005. Proceedings. IEEE International, pp. 171-174, Sept. 2005.

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