Design and Analysis of Two Low Power SRAM Cell Structures
Author:
Affiliation:
1. Koneru Lakshmaiah Education Foundation,Department of Electronics and Communication Engineering,Vaddeswaram, Guntur,Andhra Pradesh,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9760501/9760516/09760587.pdf?arnumber=9760587
Reference30 articles.
1. Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs
2. Stability analysis of different dual-port SRAM cells in deep submicron region using N-Curve Method
3. WL-VC SRAM: a low leakage memory circuit for deep sub-micron design
4. 90-nm Process-Variation Adaptive Embedded SRAM Modules With Power-Line-Floating Write Technique
5. A statistical test data compression technique with adaptive bit filling and AI based reordering: optimization for compression and scan power;parmar;International Journal of VLSI and Signal Processing Applications,2011
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