Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage-Reference-Cited by-同舟云学术

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Published:2006 Issue:13 Volume:3 Page:304-309
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Nakata Shunji¹

Affiliation:

1. NTT Microsystem Integration Laboratories

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/3/13/3_13_304/_pdf

Reference5 articles.

1. Observation of Coulomb-blockade oscillations by the back gate with subattofarad mutual capacitance

2. [2] S. Nakata, K. Saito, and M. Shimada, “Nonvolatile memory using Al₂O₃ film with an embedded Al-rich layer, ” Appl. Phys. Lett., vol. 87, 223110, 2005.

3. [3] E. Morifuji, T. Yoshida, H. Tsuno, Y. Kikuchi, S. Matsuda, S. Yamada, T. Noguchi, and M. Kakumu, “New guideline of Vdd and Vth scaling for 65nm technology and beyond, ” Proc. Symp. VLSI Tech. Dig., pp. 164-165, 2004.

4. The stability of adiabatic reversible logic using asymmetric tank capacitors and its application to SRAM

5. [5] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “Low-power embedded SRAM modules with expanding margins for writing, ” Proc. ISSCC Dig., pp. 480-481, 2005.

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low power SRAM using Adiabatic Logic;Journal of Physics: Conference Series;2020-12-01

2. Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices;ACM Journal on Emerging Technologies in Computing Systems;2020-07-31

3. Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage;2009 IEEE International Symposium on Circuits and Systems;2009-05

4. Adiabatic quasi 6T-SRAM with shared writing and reading ports;IEICE Electronics Express;2008