Adiabatic quasi 6T-SRAM with shared writing and reading ports

Author:

Nakata Shunji1

Affiliation:

1. NTT Microsystem Integration Laboratories

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference9 articles.

1. Observation of Coulomb-blockade oscillations by the back gate with subattofarad mutual capacitance

2. [2] S. Nakata, K. Saito, and M. Shimada, “Nonvolatile memory using Al2O3 film with an embedded Al-rich layer, ” Appl. Phys. Lett., vol. 87, p. 223110, 2005.

3. [3] E. Morifuji, T. Yoshida, H. Tsuno, Y. Kikuchi, S. Matsuda, S. Yamada, T. Noguchi, and M. Kakumu, “New guideline of Vdd and Vth scaling for 65nm technology and beyond, ” Proc. Symp. VLSI Tech. Dig., pp. 164-165, 2004.

4. Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

5. [5] L. Chang et al., “Stable SRAM Cell Design for the 32nm Node and Beyond, ”Proc. Symp. VLSI Tech. Dig., pp. 128-129, 2005.

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1. Low power SRAM using Adiabatic Logic;Journal of Physics: Conference Series;2020-12-01

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