Reconfigurable scan architecture for test power and data volume reduction-Reference-Cited by-同舟云学术

Reconfigurable scan architecture for test power and data volume reduction

Published:2017 Issue:13 Volume:14 Page:20170415-20170415
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Oh Hyunggoy¹,Kim Heetae¹,Lim Jaeil¹,Kang Sungho¹

Affiliation:

1. School of Electrical and Electronic Engineering, Yonsei University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/13/14_14.20170415/_pdf

Reference10 articles.

1. [1] P. Girard: “Survey of low-power testing of VLSI circuits,” IEEE Des. Test Comput. 19 (2002) 82 (DOI: 10.1109/MDT.2002.1003802).

2. [2] S. Ravi: “Power-aware test: Challenges and solutions,” Proc. Int. Test Conf., Lecture 2.2 (2007) 1 (DOI: 10.1109/TEST.2007.4437660).

3. [3] W. Wanget al.: “Low power logic BIST with high test effectiveness,” IEICE Electron. Express 10 (2013) 20130853 (DOI: 10.1587/elex.10.20130853).

4. [4] P. Basker and A. Arulmurugan: “Survey of low power testing of VLSI circuits,” Proc. Int. Conf. Computer Communication and Informatics (2012) 1 (DOI: 10.1109/ICCCI.2012.6158884).

5. [5] S. Leiet al.: “A unified solution to reduce test power and test volume for test-per-scan schemes,” IEICE Electron. Express 7 (2010) 1364 (DOI: 10.1587/elex.7.1364).

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