Affiliation:
1. Electrical Engineering Department, Faculty of Engineering, Razi University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference7 articles.
1. Low power and high speed multiplier design with row bypassing and parallel architecture
2. [2] H. T. Ngo and V. K. Asari, “Partitioning and gating technique for low-power multiplication in video processing applications,” Microelectronics Journal, vol. 40, no. 11, pp. 1582-1589, Nov. 2009.
3. Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
4. Low-voltage adders for power-efficient arithmetic circuits
5. [5] J. M. Rabaey, Digital integrated circuits a design perspective, Prentice Hall, 2003.
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