1. Power and Area Efficient Multi-operand Binary Tree Adder;2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP);2022-02-12
2. A mutated addition–subtraction unit to reduce the complexity of FFT;Applied Nanoscience;2022-02-11
3. A novel adder cell for ultra low voltage, ultra low power networks in nanoscale VLSI circuits;IEICE Electronics Express;2011
4. Physical implementation and test of energy recovery circuit;2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03;2003
5. Ternary BiCMOS circuit structure and its design at switch level;2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03;2003