An Effective Programmable Memory BIST for Embedded Memory-Reference-Cited by-同舟云学术

An Effective Programmable Memory BIST for Embedded Memory

Published:2009 Issue:12 Volume:E92-D Page:2508-2511
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

PARK Youngkyu¹,PARK Jaeseok¹,HAN Taewoo¹,KANG Sungho¹

Affiliation:

1. Department of Electrical and Electronic Engineering, Yonsei University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

http://www.jstage.jst.go.jp/article/transinf/E92.D/12/E92.D_12_2508/_pdf

Reference5 articles.

1. An on-chip march pattern generator for testing embedded memory cores

2. [2] D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M.S. Reorda, V. Tancorre, and M. Violante, “Exploiting programmable BIST for the diagnosis of embedded memory cores,” Proc. IEEE International Test Conference, pp.379-385, Oct. 2003.

3. [3] S. Boutobza, M. Nicolaidis, K.M. Lamara, and A. Costa, “Programmable memory BIST,” Proc. IEEE International Test Conference, Paper 45.2, Nov. 2005.

4. [4] X. Du, N. Mukherjee, W.-T. Cheng, and S. Reddy, “Full-speed field-programmable memory BIST architecture,” Proc. IEEE International Test Conference, Paper 45.3, Nov. 2005.

5. [5] X. Du, N. Mukherjee, C. Hill, W.-T. Cheng, and S. Reddy, “A field programmable memory BIST architecture supporting algorithms with multiple nested loops,” Proc. IEEE Asian Test Symposium, pp.287-292, Nov. 2006.

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3. A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory;ETRI Journal;2013-10-01

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