F-Scan: A DFT Method for Functional Scan at RTL

Author:

OBIEN Marie Engelene J.1,OHTAKE Satoshi1,FUJIWARA Hideo1

Affiliation:

1. Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference19 articles.

1. [1] H. Fujiwara, Logic Testing and Design for Testability, MIT Press, Cambridge, MA, 1985.

2. Cost-free scan: a low-overhead scan path design

3. [3] R. Gupta and M.A. Breuer, “Partial scan design of register transfer level circuits,” JETTA, vol.7, pp.25-46, 1995.

4. [4] S. Bhattacharya and S. Dey, “H-Scan: A high level alternative to full-scan testing with reduced area and test application overheads,” Proc. VLSI Test Symposium, pp.74-80, April 1996.

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis;2019 IEEE International Test Conference in Asia (ITC-Asia);2019-09

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