Partial scan design of register-transfer level circuits-Reference-Cited by-同舟云学术

Partial scan design of register-transfer level circuits

Published:1995 Issue:1-2 Volume:7 Page:25-46
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Gupta Rajesh,Breuer Melvin A.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00993312.pdf

Reference21 articles.

1. E.B. Eichelberger and T.W. Williams, ?A logic design structure for LSI testability,?Proceedings 14th Design Automation Conference, pp. 462?467, June 1977.

2. M.J.Y. Williams and J.B. Angell, ?Enhancing testability of LSI circuits via test points and additional logic,?IEEE Transactions on Computers, Vol. C-22, pp. 46?60, 1973.

3. J.H. Stewart, ?Future testing of large LSI circuit cards,?Digest of Papers, IEEE Semiconductor Test Conference, pp. 6?15, October 1977.

4. S. Funatsu, N. Wakatsuki, and A. Yamada, ?Designing digital circuits with easily testable consideration,?Digest of Papers, IEEE Semiconductor Test Conference, pp. 98?102, 1978.

5. M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design. W.H. Freeman & Co., New York, 1990.

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