A Methodology for the Design of MOS Current-Mode Logic Circuits-Reference-Cited by-同舟云学术

A Methodology for the Design of MOS Current-Mode Logic Circuits

Published:2010 Issue:2 Volume:E93.C Page:172-181
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

CARUSO Giuseppe¹,MACCHIARELLA Alessio²

Affiliation:

1. Dipartimento di Ingegneria Elettrica, Elettronica e delle Telecomunicazioni, Università di Palermo

2. Dipartimento di Fisica della Materia e Ingegneria Elettronica, Università di Messina

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E93.C/2/E93.C_2_172/_pdf

Reference24 articles.

1. [1] M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol.E75-C, no.10, pp.1181-1187, Oct. 1992.

2. [2] C.H. Park, O. Kim, and B. Kim, “A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching,” IEEE J. Solid-State Circuits, vol.36, no.5, pp.777-783, May 2001.

3. [3] J. Cao, M. Green, A. Momtaz, K. Vakilian, D. Chung, K.C. Jen, M. Caresosa, X. Wang, W.G. Tan, Y. Cai, L. Fujimori, and A. Hairapetian, “OC-192 transmitter and receiver in standard 0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol.37, no.12, pp.1768-1780, Dec. 2002.

4. [4] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector,” IEEE J. Solid-State Circuits, vol.38, no.1, pp.13-21, Jan. 2003.

5. [5] D. Kehrer, H. Wohlmuth, H. Knapp, M. Wurzer, and A. Scholtz, “40.Gb/s 2: 1 multiplexer and 1: 2 demultiplexer in 120nm standard CMOS,” IEEE J. Solid-State Circuits, vol.38, no.11, pp.1830-1837, Nov. 2003.

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