A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates-Reference-Cited by-同舟云学术

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A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates

Published:2013 Issue:17 Volume:10 Page:20130599-20130599
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Caruso Giuseppe¹

Affiliation:

1. Dipartimento di Energia, Ingegneria dell'Informazione e Modelli Matematici, Università di Palermo

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/10/17/10_10.20130599/_pdf

Reference5 articles.

1. [1] G. Caruso and A. Macchiarella: IEICE Trans. Electron. E93-C [2] (2010) 172.

2. [2] M. Alioto and G. Palumbo: IEEE Circuits Syst. Mag. 6 [4] (2006) 42.

3. [3] D. M. Binkley: Proc. 14th Int. Conf. on MIXDES ‘07 (2007) 47.

4. [4] Y. Aizik and A. Kolodny: IEEE 25th Convention of Electrical and Electronics Engineers in Israel (2008) 1.

5. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL) circuits for ultra-low-power applications;Microelectronics Journal;2018-04

2. Accurate delay models of CMOS CML circuits for design optimization;Analog Integrated Circuits and Signal Processing;2014-12-05

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