40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

Author:

Kehrer D.,Wohlmuth H.,Knapp H.,Wurzer M.,Scholtz A.L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 34 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application;2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS);2017-12

2. 40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-04

3. Multiple logic styles for low power 4:1 multiplexer in 45 nm technology;International Journal of Signal and Imaging Systems Engineering;2015

4. Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-On-Chip;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-10

5. High performance, low power 200 Gb/s 4:1 MUX with TGL in 45 nm technology;Applied Nanoscience;2013-03-16

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