Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM
Author:
Affiliation:
1. Kobe University
2. JST CREST
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E96.C/4/E96.C_528/_pdf
Reference31 articles.
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4. [4] B. Stackhouse, S. Bhimji, C. Bostak, D. Bradley, B. Cherkauer, J. Desai, E. Francom, M. Gowan, P. Gronowski, D. Krueger, C. Morganti, and S. Troyer, “A 65nm 2-billion transistor quad-core Itanium processor,” IEEE J. Solid-State Circuits, vol.44, no.1, pp.18-31, Jan. 2009.
5. [5] M. Floyd, M. Allen-Ware, K. Rajamani, B. Brock, C. Lefurgy, A.J. Drake, L. Pesantez, T. Gloekler, J.A. Tierno, P. Bose, and A. Buyuktosunoglu, “Introducing the adaptive energy management features of the Power7 chip,” IEEE Micro, vol.31, no.2, pp.60-75, March 2011.
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