A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing-Reference-Cited by-同舟云学术

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing

Published:2012 Issue:11 Volume:E95.C Page:1799-1809
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

CHAO I-Jen¹,HSU Chung-Lun¹,LIU Bin-Da¹,CHANG Soon-Jyu¹,HUANG Chun-Yueh²,TING Hsin-Wen³

Affiliation:

1. Department of Electrical Engineering, National Cheng Kung University

2. Department of Electrical Engineering, National University of Tainan

3. Department of Electronics Engineering, National Kaohsiung University of Applied Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E95.C/11/E95.C_1799/_pdf

Reference14 articles.

1. [2] N. Waki, H. Sato, and A. Hyogo, “Input-feedforward two-path band-pass delta-sigma modulator based on horizontal or vertical opamp sharing technique,” IEICE Trans. Fundamentals, vol.E91-A, no.2, pp.443-453, Feb. 2008.

2. [3] O.A. Adeniran and A. Demoshenous, “Constant-resistance CMOS input sampling switch for GSM/WCDMA high dynamic range ΔΣ modulators,” IEEE Trans. Circuits Syst. I, vol.55, no.11, pp.3234-3245, Nov. 2008.

3. [4] Y. Fujimoto, Y. Kanazawa, P.L. Re, and M. Miyamoto, “An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for digital TV receivers,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers., pp.76-77, Feb. 2006.

4. [5] J. Koh, Y. Chio, and G. Gomez, “A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2nd-order ΔΣ ADC for WCDMA in 90nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers., pp.170-171, Feb. 2005.

5. Wideband low-distortion delta-sigma ADC topology

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