A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer
Author:
Affiliation:
1. Tokyo City University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E101.C/7/E101.C_480/_pdf
Reference18 articles.
1. [1] Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, “An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS,” IEEE J. Solid-State Circuits, vol.51, no.12, pp.2928-2940, Dec. 2016. 10.1109/jssc.2016.2592623
2. [2] W.-H. Tseng, W.-L. Lee, C.-Y. Huang, and P.-C. Chiu, “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,” IEEE J. Solid-State Circuits, vol.51, no.10, pp.2222-2231, Oct. 2016. 10.1109/jssc.2016.2582861
3. [3] R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2004.
4. [4] K. Lee, M.R. Miller, and G.C. Temes, “An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and-98 dB THD,” IEEE J. Solid-State Circuits, pp.2202-2211, Aug. 2009.
5. [5] B. Wu, S. Zhu, B. Xu, and Y. Chiu, “A 24.7mW 45MHz-BW 75.3dB-SNDR SAR Assisted CT ΔΣModulator with 2nd-Order Noise Coupling in 65nm CMOS,” ISSCC Dig. Tech, pp.270-271, Feb. 2016. 10.1109/isscc.2016.7418011
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1. A new17-bit 105.5-dB dynamic range 2-1 cascaded SAR-based ΔΣ modulator using single-bit DAC for audio applications;AEU - International Journal of Electronics and Communications;2020-12
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