A Precise Model for Cross-Point Memory Array
Author:
Affiliation:
1. Toshiba
2. Toyo University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E99.C/1/E99.C_119/_pdf
Reference15 articles.
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2. [2] C.J. Amsinck, N.H.D. Spigna, D.P. Nackashi, and P.D. Franzon, “Scaling constraints in nanoelectronic random-access memories,” Nanotechnology, vol.16, no.10, pp.2251-2260, Aug. 2005.
3. [3] A. Flocke and T.G. Noll, “Fundamental analysis of resistive nano-crossbars for the use in hybrid nano/CMOS-memory,” Proc. 33rd European Solid-State Circuits Conf., Munich, Germany, pp.328-331, Sept. 2007.
4. [4] J. Liang, S. Yeh, S.S. Wong, and H.-S. Philip Wong, “Scaling challenges for the cross-point resistive memory array to sub-10nm node-An interconnect perspective,” Proc. 4th IEEE International Memory Workshop, pp.1-4, May 2012.
5. [5] A. Chen, “A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics,” IEEE Trans. Electron Devices, vol.60, no.4, pp.1318-1326, April 2013.
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1. A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array;IEICE Transactions on Electronics;2017
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