Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs-Reference-Cited by-同舟云学术

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs

Published:2021-01-25 Issue:2 Volume:18 Page:20200420-20200420
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Song Tai¹,Liang Huaguo¹,Huang Zhengfeng¹,Ni Tianming²,Sun Ying³

Affiliation:

1. School of Electronic Science and Applied Physics, Hefei University of Technology

2. Department of Electrical Engineering, Anhui Polytechnic University

3. Department of Computer Science and Technology, Pingdingshan Polytechnic college

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/18/2/18_17.20200420/_pdf

Reference30 articles.

1. [1] M.B. Alawieh, et al.: “Wafer map defect patterns classification using deep selective learning,” 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC) (2020) (DOI: 10.1109/dac18072.2020.9218580).

2. [2] T. Song, et al.: “Novel application of deep learning for adaptive testing based on long short-term memory,” 2019 IEEE 37th VTS (2019) (DOI: 10.1109/vts.2019.8758628).

3. [3] H.-G. Stratigopoulos and C. Streitwieser: “Adaptive test with test escape estimation for mixed-signal ICs,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 37 (2018) 2125 (DOI: 10.1109/TCAD.2017.2783302).

4. [4] Semiconductor Industry Association: “International roadmap for devices and system (IRDS),” (2020).

5. [5] T. Song, et al.: “Pattern reorder for test cost reduction through improved SVMRANK algorithm,” IEEE Access 8 (2020) 147965 (DOI: 10.1109/access.2020.3016039).

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