1. [1] H. Tanaka, et al.: “Bit cost scalable technology with punch and plug process for ultra high density flash memory,” 2007 IEEE Symposium on VLSI Technology (2007) (DOI: 10.1109/VLSIT.2007.4339708).
2. [2] R. Micheloni, et al.: “Array architectures for 3-D NAND flash memories,” Proc. IEEE 105 (2017) 1634 (DOI: 10.1109/JPROC.2017.2697000).
3. [3] K. Parat and A. Goda: “Scaling trends in NAND flash,” 2018 IEEE International Electron Devices Meeting (IEDM) (2018) (DOI: 10.1109/IEDM.2018.8614694).
4. [4] A. Goda: “3-D NAND technology achievements and future scaling perspectives,” IEEE Trans. Electron Devices 67 (2020) 1373 (DOI: 10.1109/TED.2020.2968079).
5. [5] D. Kang, et al.: “256 Gb 3 b/cell V-NAND flash memory with 48 stacked WL layers,” IEEE J. Solid-State Circuits 52 (2016) 210 (DOI: 10.1109/JSSC.2016.2604297).