472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device-Reference-Cited by-同舟云学术

472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device

Published:2011 Issue:9 Volume:8 Page:676-683
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Lee Jeong-Gun¹,Lee Deok-Young¹,Oh Myeong-Hoon²,Ko Young-Woong¹

Affiliation:

1. Dept. of Computer Engineering, Hallym University

2. Electronics and Telecommunications Research Institute

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/8/9/8_9_676/_pdf

Reference8 articles.

1. [1] Semiconductor Industry Association, “International Technology Roadmap for Semiconductor,”[Online] http://www.itrs.net/links/2009ITRS/ Home2009.htm

2. [2] S. Hauck, S. Burns, G. Borriello, and C. Ebeling, “An FPGA for implementing asynchronous circuits,” IEEE Des. Test. Comput., vol. 11, no. 3, pp. 60-69, 1994.

3. [3] A. Royal and P. Y. K. Cheung, “Globally asynchronous locally synchronous FPGA architectures,” Field Programmable Logic and Applications, LNCS 2778, 2003.

4. [4] C. LaFrieda, B. Hill, and R. Manohar, “An Asynchronous FPGA with Two-Phase Enable-Scaled Routing,” Proc. IEEE Int. Symp. Asynchronous Circuits Syst., May 2010.

5. [5] E. Brunvand, M. Michell, and K. Smith, “A comparison of self-timed design using FPGA, CMOS, and GaAs technologies,” Proc. Int. Conf. Computer Design, pp. 76-80, Oct. 1992.

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