An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design-Reference-Cited by-同舟云学术

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

Published:2015 Issue:7 Volume:E98.A Page:1376-1391
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

ABE Shin-ya¹,SHI Youhua²,USAMI Kimiyoshi³⁴¹,YANAGISAWA Masao³,TOGAWA Nozomu¹

Affiliation:

1. Department of Computer Science and Engineering, Waseda University

2. Waseda Institute for Advanced Study, Waseda University

3. Department of Electronic and Photonic Systems, Waseda University

4. Department of Information Science and Engineering, Shibaura Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E98.A/7/E98.A_1376/_pdf

Reference17 articles.

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3. [3] K. Nose, A. Shibayama, H. Kodama, M. Mizuno, M. Edahiro, and N. Nishi, “Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core socs,” ISSCC Dig. Tech. Papers, pp.296-599, 2005.

4. [4] G. Lhairech-Lebreton, P. Coussy, and E. Martin, “Hierarchical and multiple-clock domain high-level synthesis for low-power design on fpga,” Proc. FPL'10, pp.464-468, 2010.

5. [5] J. Jeon, D. Kim, D. Shin, and K. Choi, “High-level synthesis under multi-cycle interconnect delay,” Proc. ASP-DAC'01, pp.662-667, 2001.